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8. Sep, 1998 ML63326 PRELIMINARY
ML63326
4-Bit Microcontroller with built-in Voice Synthesis and 1024-Dot LCD Drivers
GENERAL DESCRIPTION
The ML63326 is a low power 4-bit microcontroller which incorporates the OKI original CPU core nX-4/250 and provides a minimum instruction execution time of 1s (@2MHz). It contains 24K-word program memory, 1536-nibble data memory, 4-bit input port, four 4-bit output ports, five 4-bit and 2-bit input-output ports, shift register, LCD driver for up to 1024 segments, and voice synthesis, including 1 megabit mask ROM for speech data, a 12-bit D/A converter and low-pass filter internally. Speech ROM size can be expanded externally with further 4 megabits. The ML63326 is suitable for applications such as games, toys, clocks etc. which use an LCD display and voice synthesis.
FEATURES
* Rich instruction set 439 instructions Transfer, rotate, increment, decrement, arithmetic operations, comparison, logic operations, mask operations, bit operations, ROM table reference, external memory transfer, stack operations, flag operations, branch, conditional branch, call/return, control. * Rich selection of addressing modes Indirect addressing of four data memory types, with current bank register, extra bank register, HL register and XY register. Data memory bank internal direct addressing mode. * Processing speed Two clocks per machine cycle, with most instructions executed in one machine cycle. Minimum instruction execution time : 61s ( @32.768kHz system clock ) 1s ( @2MHz system clock: 1/2 of high-speed clock ) * Clock generation circuit Low-speed clock: High-speed clock: : 32.768kHz crystal oscillator, or 32kHz 40% (@1M 10%), RC oscillator (by mask option) : 4MHz (max.) crystal oscillator, or 2MHz 40% (@20k 5%) RC oscillator (by software selection)
* Program memory space 24K words Basic instruction length is 16 bits / 1 word * Data memory space 1536 nibbles * External data memory space 64kbyte ( expandable ) * Stack level Call stack level : 16 levels Register stack level : 16 levels
8.Sep,1998 ML63326 PRELIMINARY * I/O ports Input ports: Selectable as input with pull-up resistance/ input with pull-down resistor / high-impedance input Output ports: Selectable as P-channel open drain output / N-channel open drain output / CMOS output / high-impedance output Input-output ports: Selectable as input with pull-up resistance / input with pull-down resistance / highimpedance input Selectable as P-channel open drain output / N-channel open drain output / CMOS output / high-impedance output Can be interfaced with external peripherals that use a different power supply than this device uses. Number of ports: Input ports : 1 port x 4 bits Output port : 4 ports x 4 its Input-output port : 5 ports x 4 bits and 1 port x 2 bits * Voice synthesis Algorithm : 4-bit ADPCM / Oki non-linear 8-bit PCM / 8-bit PCM Voice synthesis data memory: Internal ROM : 1 Mbit mask ROM (128k bytes) External ROM : 4 Mbit ROM (512k bytes max.) Sampling frequencies (at clock frequency 4.096MHz) 4.0kHz, 5.3kHz, 6.4kHz, 8.0kHz, 10.7kHz, 12.8kHz, 16.0kHz 12-bit D/A converter Low-pass filter * Melody output function Two systems (one is in voice synthesis portion, the other is in microcontoroller portion) MD, MDB output ports are selected from two systems Melody output in voice synthesis portion can put out to AOUT/AOUTB output ports * LCD driver Number of segments : 1024 Max. (64SEG x 16COM) 1/1 to 1/16 duty 1/4 or 1/5 bias (regulator built-in) Selectable as all-on mode/ all-off mode/ power down mode/ normal display mode Adjustable contrast * Reset function Reset through RESET pin Power-on reset Reset to low-speed oscillation halt * Battery check Low-voltage supply check Criterion voltage : Can be selected as 2.40 0.20V * Timers and Counters 8-bit timer x 4 Selectable to auto-reload mode/ capture mode/ clock frequency measurement mode Watchdog timer x 1 100Hz timer x 1 15-bit time-base counter x 1 1, 2, 4, 8, 16, 32, 64, and 128Hz signals can be read
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8.Sep,1998 ML63326 PRELIMINARY * Shift register Shift clock Data length * Interrupt sources External interrupt Internal interrupt * Operating voltage +2.0 to 5.5V * Package Chip Chip size Chip thickness Fig.1 shows PAD layout image. Minimum pad pitch Bonding pad size Pad size
: 1 x or 1/2 x system clock, external clock : 8 bits :3 : 12 (watchdog timer x 1, time base x 4, 100Hz timer x 1, timer x 4, shift-register x 1, melody x 1), (watchdog timer interrupt is a nonmaskable interrupt )
: ( Product name : ML63326 - xxx ) xxx indicates a code number. : TBA : 350 m (typ.) : xxx m (a) : 100m x 100m (b x c) : 110m x 110m (d x e)
a
d
b
c e
Fig.1 PAD layout
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8. Sep, 1998 ML63326 PRELIMINARY
BLOCK DIAGRAM
An asterisk (*) indicates the port secondary function. indicates that the power is supplied to the circuits corresponding to the signal names inside from VDDI ( power supply for interface ) .
nX-4/250 TIMING CONTROL SP RSP STACK CAL.S:16-level REG.S:16-level RESET TST1 TST2 XT0 XT1 OSC0 OSC1 VDDH VDD CB1 CB2 VDD5 VDD4 VDD3 VDD2 VDD1 C1 C2 VDDL AOUT AOUTB MD MDB VREF Multiplexer 12bit DAC REGULATOR DATA BUS BLD INT 1 INT 1 BIAS INT 1 MELODY LCD & DSPR VOICE INTERFACE WDT 100Hz TC OUTPUT PORT INT 2 I/O PORT ALU MIE INSTRUCTION DECODER IR INT 4 RESET TEST OSCL INT OSCH 4 TBC RAM 1536x4bits INT326 INT 1 SFT INT 1 CBR EBR H X L Y C RA A G Z BUS CONTROL PC ROM 24Kx16bits
EXTMEM
D0 to D7* A0 to A15* RD* WR*
TIMER 8bitx4
TM0CAP/TM1CAP* TM0OVF/TM1OVF* T02CK* T13CK* SIN* SOUT* SCLK*
INPUT PORT
P0.0 to P0.3 P4.0 to P4.3 P5.0 to P5.3 P6.0 to P6.3 P7.0 to P7.3 P8.0,P8.1 P9.0 to P9.3 PA.0 to PA.3 PB.0 to PB.3 PE.0 to PE.3 PF.0 to PF.3 COM1 to 16 SEG0 to 63 VDDI VSS BUSY
LPF
Phrase Address Latch
Multiplexer
PCM Synthesizer
Address Controller
MELODY
ADPCM Synthesizer
17bit Multiplexer
1Mbit ROM The voice synthesis portion
17bit Address Counter
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